《数字集成电路设计:从VLSI体系结构到CMOS制造(英文版)》作者:Hubert Kaeslin著

数字集成电路设计:从VLSI体系结构到CMOS制造(英文版)

  • 内容简介:

      《数字集成电路设计:从VLSI体系结构到CMOS制造(英文版)》从架构与算法讲起,介绍了功能验证、VHDL建模、同步电路设计、异步数据获取、能耗与散热、信号完整性、物理设计、设计验证等必备技术,还讲解了VLSI经济运作与项目管理,并简单阐释了CMOS技术的基础知识,全面覆盖了数字集成电路的整个设计开发过程。
      《数字集成电路设计:从VLSI体系结构到CMOS制造(英文版)》既可作为高等院校微电子、电子技术等相关专业高年级师生和研究生的参考教材,也可供半导体行业工程师参考。

  • 作者简介:

      HubertKaeslin,1985年于瑞士苏黎世联邦理工学院获得博士学位,现为该校微电子设计中心的负责人,具有20多年教授VLSI的丰富经验。

  • 目录:

    Chapter1 IntroductiontoMicroelectronics 1
    1.1 Economicimpact 1
    1.2 Conceptsandterminology 4
    1.2.1 TheGuinnessbookofrecordspointofview 4
    1.2.2 Themarketingpointofview 5
    1.2.3 Thefabricationpointofview 6
    1.2.4 Thedesignengineerspointofview 10
    1.2.5 Thebusinesspointofview 17
    1.3 DesignflowindigitalVLSI 18
    1.3.1 TheY-chart,amapofdigitalelectronicsystems 18
    1.3.2 MajorstagesinVLSIdesign 19
    1.3.3 Celllibraries 28
    1.3.4 Electronicdesignautomationsoftware 29
    1.4 Field-programmablelogic 30
    1.4.1 Configurationtechnologies 30
    1.4.2 Organizationofhardwareresources 32
    1.4.3 Commercialproducts 35
    1.5 Problems 37
    1.6 AppendixI:Abriefglossaryoflogicfamilies 38
    1.7 AppendixII:Anillustratedglossaryofcircuit-relatedterms 40
    Chapter2 FromAlgorithmstoArchitectures 44
    2.1 Thegoalsofarchitecturedesign 44
    2.1.1 Agenda 45
    2.2 Thearchitecturalantipodes 45
    2.2.1 WhatmakesanalgorithmsuitableforadedicatedVLSIarchitecture? 50
    2.2.2 Thereisplentyoflandbetweenthearchitecturalantipodes 53
    2.2.3 Assembliesofgeneral-purposeanddedicatedprocessingunits 54
    2.2.4 Coprocessors 55
    2.2.5 Application-specificinstructionsetprocessors 55
    2.2.6 Configurablecomputing 58
    2.2.7 Extendableinstructionsetprocessors 59
    2.2.8 Digest 60
    2.3A transformapproachtoVLSIarchitecturedesign 61
    2.3.1 Thereisroomforremodellinginthealgorithmicdomain 62
    2.3.2 …andthereisroominthearchitecturaldomain 64
    2.3.3 SystemsengineersandVLSIdesignersmustcollaborate 64
    2.3.4 Agraph-basedformalismfordescribingprocessingalgorithms 65
    2.3.5 Theisomorphicarchitecture 66
    2.3.6 Relativemeritsofarchitecturalalternatives 67
    2.3.7 Computationcycleversusclockperiod 69
    2.4 Equivalencetransformsforcombinationalcomputations 70
    2.4.1 Commonassumptions 71
    2.4.2 Iterativedecomposition 72
    2.4.3 Pipelining 75
    2.4.4 Replication 79
    2.4.5 Timesharing 81
    2.4.6 Associativitytransform 86
    2.4.7 Otheralgebraictransforms 87
    2.4.8 Digest 87
    2.5 Optionsfortemporarystorageofdata 89
    2.5.1 Dataaccesspatterns 89
    2.5.2 Availablememoryconfigurationsandareaoccupation 89
    2.5.3 Storagecapacities 90
    2.5.4 Wiringandthecostsofgoingoff-chip 91
    2.5.5 Latencyandtiming 91
    2.5.6 Digest 92
    2.6 Equivalencetransformsfornonrecursivecomputations 93
    2.6.1 Retiming 94
    2.6.2 Pipeliningrevisited 95
    2.6.3 Systolicconversion 97
    2.6.4 Iterativedecompositionandtime-sharingrevisited 98
    2.6.5 Replicationrevisited 98
    2.6.6 Digest 99
    2.7 Equivalencetransformsforrecursivecomputations 99
    2.7.1 Thefeedbackbottleneck 100
    2.7.2 Unfoldingoffirst-orderloops 101
    2.7.3 Higher-orderloops 103
    2.7.4 Time-variantloops 105
    2.7.5 Nonlinearorgeneralloops 106
    2.7.6 Pipelineinterleavingisnotanequivalencetransform 109
    2.7.7 Digest 111
    2.8 Generalizationsofthetransformapproach 112
    2.8.1 Generalizationtootherlevelsofdetail 112
    2.8.2 Bit-serialarchitectures 113
    2.8.3 Distributedarithmetic 116
    2.8.4 Generalizationtootheralgebraicstructures 118
    2.8.5 Digest 121
    2.9 Conclusions 122
    2.9.1 Summary 122
    2.9.2 Thegrandarchitecturalalternativesfromanenergypointofview 124
    2.9.3 Aguidetoevaluatingarchitecturalalternatives 126
    2.10 Problems 128
    2.11 AppendixI:Abriefglossaryofalgebraicstructures 130
    2.12 AppendixII:AreaanddelayfiguresofVLSIsubfunctions 133
    Chapter3 FunctionalVerification 136
    3.1 Howtoestablishvalidfunctionalspecifications 137
    3.1.1 Formalspecification 138
    3.1.2 Rapidprototyping 138
    3.2 Developinganadequatesimulationstrategy 139
    3.2.1 Whatdoesittaketouncoveradesignflawduringsimulation? 139
    3.2.2 Stimulationandresponsecheckingmustoccurautomatically 140
    3.2.3 Exhaustiveverificationremainsanelusivegoal 142
    3.2.4 Allpartialverificationtechniqueshavetheirpitfalls 143
    3.2.5 Collectingtestcasesfrommultiplesourceshelps 150
    3.2.6 Assertion-basedverificationhelps 150
    3.2.7 Separatingtestdevelopmentfromcircuitdesignhelps 151
    3.2.8 Virtualprototypeshelptogenerateexpectedresponses 153
    3.3 Reusingthesamefunctionalgaugethroughouttheentiredesigncycle 153
    3.3.1 Alternativewaystohandlestimuliandexpectedresponses 155
    3.3.2 Modulartestbenchdesign 156
    3.3.3 Awell-definedscheduleforstimuliandresponses 156
    3.3.4 Trimmingruntimesbyskippingredundantsimulationsequences 159
    3.3.5 Abstractingtohigher-leveltransactionsonhigher-leveldata 160
    3.3.6 Absorbinglatencyvariationsacrossmultiplecircuitmodels 164
    3.4 Conclusions 166
    3.5 Problems 168
    3.6 AppendixI:Formalapproachestofunctionalverification 170
    3.7 AppendixII:Derivingacoherentscheduleforsimulationandtest 171
    Chapter4 ModellingHardwarewithVHDL 175
    4.1 Motivation 175
    4.1.1 Whyhardwaresynthesis? 175
    4.1.2 WhatarethealternativestoVHDL? 176
    4.1.3 WhataretheoriginsandaspirationsoftheIEEE1076standard? 176
    4.1.4 Whybotherlearninghardwaredescriptionlanguages? 179
    4.1.5 Agenda 180
    4.2 KeyconceptsandconstructsofVHDL 180
    4.2.1 Circuithierarchyandconnectivity 181
    4.2.2 Concurrentprocessesandprocessinteraction 185
    4.2.3 Adiscretereplacementforelectricalsignals 192
    4.2.4 Anevent-basedconceptoftimeforgoverningsimulation 200
    4.2.5 Facilitiesformodelparametrization 211
    4.2.6 Conceptsborrowedfromprogramminglanguages 216
    4.3 PuttingVHDLtoserviceforhardwaresynthesis 223
    4.3.1 Synthesisoverview 223
    4.3.2 Datatypes 224
    4.3.3 Registers,finitestatemachines,andothersequentialsubcircuits 225
    4.3.4 RAMs,ROMs,andothermacrocells 231
    4.3.5 Circuitsthatmustbecontrolledatthenetlistlevel 233
    4.3.6 Timingconstraints 234
    4.3.7 Limitationsandcaveatsforsynthesis 238
    4.3.8 Howtoestablisharegistertransfer-levelmodelstepbystep 238
    4.4 PuttingVHDLtoserviceforhardwaresimulation 242
    4.4.1 Ingredientsofdigitalsimulation 242
    4.4.2 Anatomyofagenerictestbench 242
    4.4.3 Adaptingtoadesignproblemathand 245
    4.4.4 TheVITALmodellingstandardIEEE1076.4 245
    4.5 Conclusions 247
    4.6 Problems 248
    4.7 AppendixI:BooksandWebPagesonVHDL 250
    4.8 AppendixII:Relatedextensionsandstandards 251
    4.8.1 ProtectedsharedvariablesIEEE1076a 251
    4.8.2 Theanalogandmixed-signalextensionIEEE1076.1 252
    4.8.3 MathematicalpackagesforrealandcomplexnumbersIEEE1076.2 253
    4.8.4 ThearithmeticpackagesIEEE1076.3 254
    4.8.5 AlanguagesubsetearmarkedforsynthesisIEEE1076.6 254
    4.8.6 Thestandarddelayformat(SDF)IEEE1497 254
    4.8.7 Ahandycompilationoftypeconversionfunctions 255
    4.9 AppendixIII:ExamplesofVHDLmodels 256
    4.9.1 Combinationalcircuitmodels 256
    4.9.2 Mealy,Moore,andMedvedevmachines 261
    4.9.3 Statereductionandstateencoding 268
    4.9.4 Simulationtestbenches 270
    4.9.5 WorkingwithVHDLtoolsfromdifferentvendors 285
    Chapter5 TheCaseforSynchronousDesign 286
    5.1 Introduction 286
    5.2 Thegrandalternativesforregulatingstatechanges 287
    5.2.1 Synchronousclocking 287
    5.2.2 Asynchronousclocking 288
    5.2.3 Self-timedclocking 288
    5.3 WhyarigorousapproachtoclockingisessentialinVLSI 290
    5.3.1 Theperilsofhazards 290
    5.3.2 Theprosandconsofsynchronousclocking 291
    5.3.3 Clock-as-clock-canisnotanoptioninVLSI 293
    5.3.4 Fullyself-timedclockingisnotnormallyanoptioneither 294
    5.3.5 Hybridapproachestosystemclocking 294
    5.4 Thedosanddon’tsofsynchronouscircuitdesign 296
    5.4.1 Firstguidingprinciple:Dissociatesignalclasses! 296
    5.4.2 Secondguidingprinciple:Allowcircuitstosettlebeforeclocking! 298
    5.4.3 Synchronousdesignrulesatamoredetailedlevel 298
    5.5 Conclusions 306
    5.6 Problems 306
    5.7 Appendix:Onidentifyingsignals 307
    5.7.1 Signalclass 307
    5.7.2 Activelevel 308
    5.7.3 Signalingwaveforms 309
    5.7.4 Three-statecapability311
    5.7.5 Inputs,outputs,andbidirectionalterminals 311
    5.7.6 Presentstatevs.nextstate 312
    5.7.7 Syntacticalconventions 312
    5.7.8 Anoteonupper-andlower-caselettersinVHDL 313
    5.7.9 AnoteontheportabilityofnamesacrossEDAplatforms 314
    Chapter6 ClockingofSynchronousCircuits 315
    6.1 Whatisthedifficultyinclockdistribution? 315
    6.1.1 Agenda 316
    6.1.2 Timingquantitiesrelatedtoclockdistribution 317
    6.2 Howmuchskewandjitterdoesacircuittolerate? 317
    6.2.1 Basics317
    6.2.2 Single-edge-triggeredone-phaseclocking 319
    6.2.3 Dual-edge-triggeredone-phaseclocking 326
    6.2.4 Symmetriclevel-sensitivetwo-phaseclocking 327
    6.2.5 Unsymmetriclevel-sensitivetwo-phaseclocking 331
    6.2.6 Single-wirelevel-sensitivetwo-phaseclocking 334
    6.2.7 Level-sensitiveone-phaseclockingandwavepipelining 336
    6.3 Howtokeepclockskewwithintightbounds 339
    6.3.1 Clockwaveforms 339
    6.3.2 Collectiveclockbuffers 340
    6.3.3 Distributedclockbuffertrees 343
    6.3.4 Hybridclockdistributionnetworks 344
    6.3.5 Clockskewanalysis 345
    6.4 Howtoachievefriendlyinput/outputtiming 346
    6.4.1 FriendlyasopposedtounfriendlyI/Otiming 346
    6.4.2 ImpactofclockdistributiondelayonI/Otiming 347
    6.4.3 ImpactofPTVvariationsonI/Otiming 349
    6.4.4 Registeredinputsandoutputs 350
    6.4.5 Addingartificialcontaminationdelaytodatainputs 350
    6.4.6 Drivinginputregistersfromanearlyclock 351
    6.4.7 Tappingadomain’sclockfromtheslowestcomponenttherein 351
    6.4.8 “Zero-delay”clockdistributionbywayofaDLLorPLL 352
    6.5 Howtoimplementclockgatingproperly 353
    6.5.1 Traditionalfeedback-typeregisterswithenable 353
    6.5.2 Acrudeandunsafeapproachtoclockgating 354
    6.5.3 Asimpleclockgatingschemethatmayworkundercertainconditions 355
    6.5.4 Safeclockgatingschemes 355
    6.6 Summary 357
    6.7 Problems 361
    Chapter7 AcquisitionofAsynchronousData 364
    7.1 Motivation 364
    7.2 Thedataconsistencyproblemofvectoredacquisition 366
    7.2.1 Plainbit-parallelsynchronization 366
    7.2.2 Unit-distancecoding 367
    7.2.3 Suppressionofcrossoverpatterns 368
    7.2.4 Handshaking 369
    7.2.5 Partialhandshaking 371
    7.3 Thedataconsistencyproblemofscalaracquisition 373
    7.3.1 Nosynchronizationwhatsoever 373
    7.3.2 Synchronizationatmultipleplaces 373
    7.3.3 Synchronizationatasingleplace 373
    7.3.4 Synchronizationfromaslowclock 374
    7.4 Metastablesynchronizerbehavior 374
    7.4.1 Marginaltriggeringandhowitbecomesmanifest 374
    7.4.2 Repercussionsoncircuitfunctioning 378
    7.4.3 Astatisticalmodelforestimatingsynchronizerreliability 379
    7.4.4 Plesiochronousinterfaces 381
    7.4.5 Containmentofmetastablebehavior 381
    7.5 Summary 384
    7.6 Problems 384
    Chapter8 Gate-andTransistor-LevelDesign 386
    8.1 CMOSlogicgates 386
    8.1.1 TheMOSFETasaswitch 387
    8.1.2 Theinverter 388
    8.1.3 SimpleCMOSgates 396
    8.1.4 Compositeorcomplexgates 399
    8.1.5 Gateswithhigh-impedancecapabilities 403
    8.1.6 Paritygates 406
    8.1.7 Adderslices 407
    8.2 CMOSbistables 409
    8.2.1 Latches 410
    8.2.2 Functionlatches 412
    8.2.3 Single-edge-triggeredflip-flops 413
    8.2.4 Themotherofallflip-flops 415
    8.2.5 Dual-edge-triggeredflip-flops 417
    8.2.6 Digest 418
    8.3 CMOSon-chipmemories 418
    8.3.1 StaticRAM 418
    8.3.2 DynamicRAM 423
    8.3.3 Otherdifferencesandcommonalities 424
    8.4 ElectricalCMOScontraptions 425
    8.4.1 Snapper 425
    8.4.2 Schmitttrigger 426
    8.4.3 Tie-offcells 427
    8.4.4 Fillercellorfillcap 428
    8.4.5 Levelshiftersandinput/outputbuffers 429
    8.4.6 Digitallyadjustabledelaylines 429
    8.5 Pitfalls 430
    8.5.1 Bussesandthree-statenodes 430
    8.5.2 Transmissiongatesandotherbidirectionalcomponents 434
    8.5.3 Whatdowemeanbysafedesign? 437
    8.5.4 Microprocessorinterfacecircuits 438
    8.5.5 Mechanicalcontacts 440
    8.5.6 Conclusions 440
    8.6 Problems 442
    8.7 AppendixI:SummaryonelectricalMOSFETmodels 445
    8.7.1 Namingandcountingconventions 445
    8.7.2 TheSahmodel 446
    8.7.3 TheShichman–Hodgesmodel 450
    8.7.4 Thealpha-power-lawmodel 450
    8.7.5 Second-ordereffects 452
    8.7.6 Effectsnotnormallycapturedbytransistormodels 455
    8.7.7 Conclusions 456
    8.8 AppendixII:TheBipolarJunctionTransistor 457
    Chapter9 EnergyEfficiencyandHeatRemoval 459
    9.1 WhatdoesenergygetdissipatedforinCMOScircuits? 459
    9.1.1 Charginganddischargingofcapacitiveloads 460
    9.1.2 Crossovercurrents 465
    9.1.3 Resistiveloads 467
    9.1.4 Leakagecurrents 468
    9.1.5 Totalenergydissipation 470
    9.1.6 CMOSvoltagescaling 471
    9.2 Howtoimproveenergyefficiency 474
    9.2.1 Generalguidelines 474
    9.2.2 Howtoreducedynamicdissipation 476
    9.2.3 Howtocounteractleakage 482
    9.3 Heatflowandheatremoval 488
    9.4 AppendixI:Contributionstonodecapacitance 490
    9.5 AppendixII:Unorthodoxapproaches 491
    9.5.1 Subthresholdlogic 491
    9.5.2 Voltage-swing-reductiontechniques 492
    9.5.3 Adiabaticlogic 492
    Chapter10 SignalIntegrity 495
    10.1 Introduction 495
    10.1.1 Howdoesnoiseenterelectroniccircuits? 495
    10.1.2 Howdoesnoiseaffectdigitalcircuits? 496
    10.1.3 Agenda 499
    10.2 Crosstalk 499
    10.3 Groundbounceandsupplydroop 499
    10.3.1 Couplingmechanismsduetocommonseriesimpedances 499
    10.3.2 Wheredolargeswitchingcurrentsoriginate? 501
    10.3.3 Howsevereistheimpactofgroundbounce? 501
    10.4 Howtomitigategroundbounce 504
    10.4.1 Reduceeffectiveseriesimpedances 505
    10.4.2 Separatepollutersfrompotentialvictims 510
    10.4.3 Avoidexcessiveswitchingcurrents 513
    10.4.4 Safeguardnoisemargins 517
    10.5 Conclusions 519
    10.6 Problems 519
    10.7 Appendix:Derivationofsecond-orderapproximation 521
    Chapter11 PhysicalDesign 523
    11.1 Agenda 523
    11.2 Conductinglayersandtheircharacteristics 523
    11.2.1 Geometricpropertiesandlayoutrules 523
    11.2.2 Electricalproperties 527
    11.2.3 Connectingbetweenlayers 527
    11.2.4 Typicalrolesofconductinglayers 529
    11.3 Cell-basedback-enddesign 531
    11.3.1 Floorplanning 531
    11.3.2 Identifymajorbuildingblocksandclockdomains 532
    11.3.3 Establishapinbudget 533
    11.3.4 Findarelativearrangementofallmajorbuildingblocks 534
    11.3.5 Planpower,clock,andsignaldistribution 535
    11.3.6 Placeandroute(P&R) 538
    11.3.7 Chipassembly 539
    11.4 Packaging 540
    11.4.1 Wafersorting 543
    11.4.2 Wafertesting 543
    11.4.3 Backgrindingandsingulation 544
    11.4.4 Encapsulation 544
    11.4.5 Finaltestingandbinning 544
    11.4.6 Bondingdiagramandbondingrules 545
    11.4.7 Advancedpackagingtechniques 546
    11.4.8 Selectingapackagingtechnique 551
    11.5 Layoutatthedetaillevel 551
    11.5.1 Objectivesofmanuallayoutdesign 552
    11.5.2 LayoutdesignisnoWYSIWYGbusiness 552
    11.5.3 Standardcelllayout 556
    11.5.4 Sea-of-gatesmacrolayout 559
    11.5.5 SRAMcelllayout 559
    11.5.6 Lithography-friendlylayoutshelpimprovefabricationyield 561
    11.5.7 Themesh,ahighlyefficientandpopularlayoutarrangement 562
    11.6 Preventingelectricaloverstress 562
    11.6.1 Electromigration 562
    11.6.2 Electrostaticdischarge 565
    11.6.3 Latch-up 571
    11.7 Problems 575
    11.8 AppendixI:GeometricquantitiesadvertizedinVLSI 576
    11.9 AppendixII:Oncodingdiffusionareasinlayoutdrawings 577
    11.10 AppendixIII:Sheetresistance 579
    Chapter12 DesignVerification 581
    12.1 Uncoveringtimingproblems 581
    12.1.1 Whatdoessimulationtellusabouttimingproblems? 581
    12.1.2 Howdoestimingverificationhelp? 585
    12.2 Howaccuratearetimingdata? 587
    12.2.1 Celldelays 588
    12.2.2 Interconnectdelaysandlayoutparasitics 593
    12.2.3 Makingrealisticassumptionsisthepoint 597
    12.3 Morestaticverificationtechniques 598
    12.3.1 Electricalrulecheck 598
    12.3.2 Codeinspection 599
    12.4 Post-layoutdesignverification 601
    12.4.1 Designrulecheck 602
    12.4.2 Manufacturabilityanalysis 604
    12.4.3 Layoutextraction 605
    12.4.4 Layoutversusschematic 605
    12.4.5 Equivalencechecking606
    12.4.6 Post-layouttimingverification 606
    12.4.7 Powergridanalysis 607
    12.4.8 Signalintegrityanalysis 607
    12.4.9 Post-layoutsimulations 607
    12.4.10 Theoverallpicture 607
    12.5 Conclusions 608
    12.6 Problems 609
    12.7 AppendixI:Cellandlibrarycharacterization 611
    12.8 AppendixII:Equivalentcircuitsforinterconnectmodelling 612
    Chapter13 VLSIEconomicsandProjectManagement 615
    13.1 Agenda 615
    13.2 Modelsofindustrialcooperation 617
    13.2.1 Systemsassembledfromstandardpartsexclusively 617
    13.2.2 Systemsbuiltaroundprogram-controlledprocessors 618
    13.2.3 Systemsdesignedonthebasisoffield-programmablelogic 619
    13.2.4 Systemsdesignedonthebasisofsemi-customASICs 620
    13.2.5 Systemsdesignedonthebasisoffull-customASICs 622
    13.3 InterfacingwithintheASICindustry 623
    13.3.1 HandoffpointsforICdesigndata 623
    13.3.2 ScopesofICmanufacturingservices 624
    13.4 Virtualcomponents 627
    13.4.1 Copyrightprotectionvs.customerinformation 627
    13.4.2 Designreusedemandsbetterqualityandmorethoroughverification 628
    13.4.3 Manyexistingvirtualcomponentsneedtobereworked 629
    13.4.4 Virtualcomponentsrequirefollow-upservices 629
    13.4.5 Indemnificationprovisions 630
    13.4.6 DeliverablesofacomprehensiveVCpackage 630
    13.4.7 Businessmodels 631
    13.5 Thecostsofintegratedcircuits 632
    13.5.1 Theimpactofcircuitsize 633
    13.5.2 Theimpactofthefabricationprocess 636
    13.5.3 Theimpactofvolume 638
    13.5.4 Theimpactofconfigurability 639
    13.5.5 Digest 640
    13.6 Fabricationavenuesforsmallquantities 642
    13.6.1 Multi-projectwafers 642
    13.6.2 Multi-layerreticles 643
    13.6.3 Electronbeamlithography 643
    13.6.4 Laserprogramming 643
    13.6.5 HardwiredFPGAsandstructuredASICs 644
    13.6.6 Costtrading 644
    13.7 Themarketside 645
    13.7.1 Ingredientsofcommercialsuccess 645
    13.7.2 Commercializationstagesandmarketpriorities 646
    13.7.3 Serviceversusproduct 649
    13.7.4 Productgrading 650
    13.8 Makingachoice 651
    13.8.1 ASICsyesorno? 651
    13.8.2 Whichimplementationtechniqueshouldoneadopt? 655
    13.8.3 Whatifnothingisknownforsure? 657
    13.8.4 Cansystemhousesaffordtoignoremicroelectronics? 658
    13.9 KeystosuccessfulVLSIdesign 660
    13.9.1 Projectdefinitionandmarketing 660
    13.9.2 Technicalmanagement 661
    13.9.3 Engineering 662
    13.9.4 Verification 665
    13.9.5 Myths 665
    13.10 Appendix:Doingbusinessinmicroelectronics 667
    13.10.1 Checklistsforevaluatingbusinesspartnersanddesignkits 667
    13.10.2 Virtualcomponentproviders 669
    13.10.3 Selectedlow-volumeproviders 669
    13.10.4 Costestimationhelps 669
    Chapter14 APrimeronCMOSTechnology 671
    14.1 TheessenceofMOSdevicephysics 671
    14.1.1 Energybandsandelectricalconduction 671
    14.1.2 Dopingofsemiconductormaterials 672
    14.1.3 Junctions,contacts,anddiodes 674
    14.1.4 MOSFETs 676
    14.2 BasicCMOSfabricationflow 682
    14.2.1 KeycharacteristicsofCMOStechnology 682
    14.2.2 Front-end-of-linefabricationsteps 685
    14.2.3 Back-end-of-linefabricationsteps 688
    14.2.4 Processmonitoring 689
    14.2.5 Photolithography 689
    14.3 Variationsonthetheme 697
    14.3.1 Copperhasreplacedaluminumasinterconnectmaterial 697
    14.3.2 Low-permittivityinterleveldielectricsarereplacingsilicondioxide 698
    14.3.3 High-permittivitygatedielectricstoreplacesilicondioxide 699
    14.3.4 StrainedsiliconandSiGetechnology 701
    14.3.5 Metalgatesboundtocomeback 702
    14.3.6 Silicon-on-insulator(SOI)technology 703
    Chapter15 Outlook 706
    15.1 EvolutionpathsforCMOStechnology 706
    15.1.1 Classicdevicescaling 706
    15.1.2 Thesearchfornewdevicetopologies 709
    15.1.3 Verticalintegration 711
    15.1.4 Thesearchforbettersemiconductormaterials 712
    15.2 IstherelifeafterCMOS? 714
    15.2.1 Non-CMOSdatastorage 715
    15.2.2 Non-CMOSdataprocessing 716
    15.3 Technologypush 719
    15.3.1 Theso-calledindustry“laws”andtheforcesbehindthem 719
    15.3.2 Industrialroadmaps 721
    15.4 Marketpull 723
    15.5 Evolutionpathsfordesignmethodology 724
    15.5.1 Theproductivityproblem 724
    15.5.2 Freshapproachestoarchitecturedesign 727
    15.6 Summary 729
    15.7 Sixgrandchallenges 730
    15.8 Appendix:Non-semiconductorstoragetechnologiesforcomparison 731
    AppendixA ElementaryDigitalElectronics 732
    A.1 Introduction 732
    A.1.1 Commonnumberrepresentationschemes 732
    A.1.2 Notationalconventionsfortwo-valuedlogic 734
    A.2 Theoreticalbackgroundofcombinationallogic 735
    A.2.1 Truthtable 735
    A.2.2 Then-cube 736
    A.2.3 Karnaughmap 736
    A.2.4 Programcodeandotherformallanguages 736
    A.2.5 Logicequations 737
    A.2.6 Two-levellogic 738
    A.2.7 Multilevellogic740
    A.2.8 Symmetricandmonotonefunctions 741
    A.2.9 Thresholdfunctions 741
    A.2.10 Completegatesets 742
    A.2.11 Multi-outputfunctions 742
    A.2.12 Logicminimization 743
    A.3 Circuitalternativesforimplementingcombinationallogic 747
    A.3.1 Randomlogic 747
    A.3.2 Programmablelogicarray(PLA) 747
    A.3.3 Read-onlymemory(ROM) 749
    A.3.4 Arraymultiplier 749
    A.3.5 Digest 750
    A.4 Bistablesandothermemorycircuits 751
    A.4.1 Flip-flopsoredge-triggeredbistables 752
    A.4.2 Latchesorlevel-sensitivebistables 755
    A.4.3 Unclockedbistables 756
    A.4.4 Randomaccessmemories(RAMs) 760
    A.5 Transientbehavioroflogiccircuits 761
    A.5.1 Glitches,aphenomenologicalperspective 762
    A.5.2 Functionhazards,acircuit-independentmechanism 763
    A.5.3 Logichazards,acircuit-dependentmechanism 764
    A.5.4 Digest 765
    A.6 Timingquantities 766
    A.6.1 Delayquantitiesapplytocombinationalandsequentialcircuits 766
    A.6.2 Timingconditionsapplytosequentialcircuitsonly 768
    A.6.3 Secondarytimingquantities 770
    A.6.4 Timingconstraintsaddresssynthesisneeds 771
    A.7 Microprocessorinput/outputtransferprotocols 771
    A.8 Summary 773
    AppendixB FiniteStateMachines 775
    B.1 Abstractautomata 775
    B.1.1 Mealymachine 776
    B.1.2 Mooremachine 777
    B.1.3 Medvedevmachine 778
    B.1.4 Relationshipsbetweenfinitestatemachinemodels 779
    B.1.5 Taxonomyoffinitestatemachines 782
    B.1.6 Statereduction 783
    B.2 Practicalaspectsandimplementationissues 785
    B.2.1 Parasiticstatesandsymbols 785
    B.2.2 Mealy-,Moore-,Medvedev-type,andcombinationaloutputbits 787
    B.2.3 Throughpathsandlogicinstability 787
    B.2.4 Switchinghazards 789
    B.2.5 Hardwarecosts 790
    B.3 Summary 793
    AppendixC VLSIDesigner’sChecklist 794
    C.1 Designdatasanity 794
    C.2 Pre-synthesisdesignverification 794
    C.3 Clocking 795
    C.4 Gate-levelconsiderations 796
    C.5 Designfortest 797
    C.6 Electricalconsiderations 798
    C.7 Pre-layoutdesignverification 799
    C.8 Physicalconsiderations 800
    C.9 Post-layoutdesignverification 800
    C.10 Preparationfortestingoffabricatedprototypes 801
    C.11 Thermalconsiderations 802
    C.12 Board-leveloperationandtesting 802
    C.13 Documentation 802
    AppendixD Symbolsandconstants 804
    D.1 Mathematicalsymbolsused 804
    D.2 Abbreviations 807
    D.3 Physicalandmaterialconstants 808
    References 811
    Index 832


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